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| DS2186 DS2186 Transmit Line Interface FEATURES PIN ASSIGNMENT TAIS ZCSEN TCLKSEL LEN0 LEN1 LEN2 VDD TTIP TRING VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 LCLK LPOS LNEG TCLK TPOS TNEG LB MTIP MRING LF * Line interface for T1 (1.544 MHz) and CEPT (2.048 MHz) primary rate networks * On-chip transmit LBO (line build out) and line drivers eliminate external components * Programmable output pulse shape supports short- and long-loop applications * Supports bipolar and unipolar input data formats * Transparent B8ZS and HDB3 zero code suppression modes * Compatible with DS2180A T1 and DS2181A CEPT Transceivers DS2141A T1 and DS2143 E1 Controllers 20-PIN DIP (300 MIL) * Companion to the DS2187 Receive Line Interface and DS2188 T1/CEPT Jitter Attenuator TAIS ZCSEN TCLKSEL LEN0 LEN1 LEN2 VDD TTIP TRING VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 LCLK LPOS LNEG TCLK TPOS TNEG LB MTIP MRING LF * Single 5V supply; low-power CMOS technology 20-PIN SOIC (300 Mil) DESCRIPTION The DS2186 T1/CEPT Transmit Line Interface Chip interfaces user equipment to North American (T1-1.544 MHz) and European (CEPT-2.048 MHz) primary rate communications networks. The device is compatible with all types of twisted pair and coax cable found in such networks. Key on-chip components include: programmable wave shaping circuitry, line drivers, remote loopback, and zero suppression logic. A line-coupling transformer is the only external component required. Short loop (DSX-1, 0 to 655 feet) and long loop (CSU; 0 dB, -7.5 dB and -15 dB) pulse templates found in T1 applications are supported. Appropriate CCITT recommendations are met in the CEPT mode. Application areas include DACS, CSU, CPE, channel banks, and PABX-to-computer interfaces such as DMI and CPI. The DS2186 supports ISDN-PRI (Primary Rate Interface) specifications. 022798 1/11 DS2186 DS2186 BLOCK DIAGRAM Figure 1 VSS LNEG LPOS LCLK TNEG TPOS TCLK LB ZCSEN TAIS TCLKSEL LEN0 LEN1 LEN2 MTIP LINE DRIVER MONITOR MRING LF VDD TTIP INPUT DATA MUX ZERO CODE SUPPRESSION CIRCUITRY WAVESHAPPING CIRCUITRY LINE DRIVERS TRING SYSTEM LEVEL INTERCONNECT Figure 2 DS2187 AVDD LCAP 10 F NC ZCSEN RCLKSEL RTIP RECEIVE PAIR 1:2 RRING LOCK AVSS DVDD RAIS AIS BPV RCL RPOS RNEG RCLK DVSS DS2180A/DS2181A RPOS RNEG RCLK SYSTEM BACKPLANE TSER RSER DS2186 VDD ZCSEN LEN0 LEN1 LEN2 TCLKSEL TRANSMIT PAIR 1.35:1 0.47 F NONPOLARIZED TAIS TTIP TRING VSS LCLK LNEG LPOS TCLK TPOS TNEG LB MTIP MRING LF TCLK TPOS TNEG RST INT CS SCLK SDO SDI SYSTEM CONTROLLER (DS5000) 022798 2/11 DS2186 PIN DESCRIPTION Table 1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYMBOL TAIS ZCSEN TCLKSEL LEN0 LEN1 LEN2 VDD TTIP, TRING VSS LF MRING, MTIP LB TYPE I I I I DESCRIPTION Transmit Alarm Indication Signal. When high, output data is forced to all ones at the TCLK (LB=0) or LCLK (LB=1) rate. Zero Code Suppression Enable. When high, B8ZS or HDB3 encoder enabled. Transmit Clock Select. Tie to VSS for 1.544 MHz (T1) applications, to VDD for 2.048 MHz (CEPT) applications. Length Select 0, 1 and 2. State determines output T1 waveform shape and characteristics. Positive Supply. 5.0 volts. Transmit Tip and Ring. Line driver outputs; connect to transmit line transformer. Signal Ground. 0.0 volts. Line Fault. Open collector active low output. Held low during an output driver fault and/or failure; tri-stated otherwise. Monitor Tip and Ring. Normally connected to TTIP and TRING. Sense inputs for line fault detection circuitry. Loopback. When high, input data is sampled at LPOS and LNEG on falling edges of LCLK; when low, input data is sampled at TPOS and TNEG on falling TCLK. Transmit Data. Sampled on falling edges of TCLK when LB=0. Transmit Clock. 1.544 MHz or 2.048 MHz primary data clock. Loopback Data. Sampled on falling edges of LCLK when LB=1. Loopback Clock. 1.544 MHz or 2.048 MHz loopback data clock. - O - O I I 15 16 17 18 19 20 TNEG, TPOS TCLK LNEG, LPOS LCLK I I I I INPUT DATA MODES Input data is sampled on the falling edge of TCLK or LCLK and can be bipolar (dual rail) or unipolar (single rail, NRZ). TPOS, TNEG and TCLK are the data and clock inputs when LB=0, LPOS, LNEG and LCLK when LB=1. TPOS and TNEG (LPOS and LNEG) must be tied together in NRZ applications. ALARM INDICATION SIGNAL When TAIS is set, an all ones code is continuously transmitted at the TCLK rate (LB=0) or the LCLK rate (LB=1). WAVE SHAPING The device supports T1 short loop (DSX-1; 0 to 655 feet), T1 long loop (CSU; 0 dB, -7.5 dB and -15 dB) and CEPT (CCITT G.703) pulse template requirements. On-chip laser trimmed delay lines clocked by either TCLK or LCLK control a precision digital-to-analog converter to build the desired waveforms, which are buffered differentially by the line drivers. ZERO CODE SUPPRESSION MODES Transmitted data is treated transparently (no zero code suppression) when ZCSEN=0. HDB3 code words replace any all-zero nibble when ZCSEN=1 and TCLKSEL=1. B8ZS code words replace any incoming all-zero byte when ZCSEN=1 and TCLKSEL=0. 022798 3/11 DS2186 The shape of the "pre-emphasized" T1 waveform is controlled by inputs LEN0, LEN1, and LEN2 (TCLKSEL=0). These control inputs allow the user to select the appropriate output pulse shape to meet DSX-1 or CSU templates over a wide variety of cable types and lengths. Those cable types include ABAM, PIC, and PULP. The CEPT mode is enabled when TCLKSEL=1. Only one output pulse shape is available in the CEPT mode; inputs LEN0, LEN1 and LEN2 can be any state except all zeros. The line coupling transformer also contributes to the pulse shape seen at the cross-connect point. Transformers for both T1 and CEPT applications must be 1:1.35. The wave shaping circuitry does not contribute significantly to output jitter (less than 0.01 UIpp broadband). Output jitter will be dominated by the jitter on TCLK or LCLK. TCLK and LCLK need only be accurate in frequency, not duty cycle. LINE DRIVERS The on-chip differential line drivers interface directly to the output transformer. To optimize device performance, length of the TTIP and TRING traces should be minimized and isolated from neighboring interconnect. FAULT PROTECTION The line drivers are fault-protected and will withstand a shorted transformer secondary (or primary) without damage. Inputs MTIP and MRING are normally tied to TTIP and TRING to provide fault monitoring capability. Output LF will transition low if 192 TCLK cycles occur without a one occurring at MTIP or MRING. LF will tri- state on the next one occurrence or two TCLK periods later, whichever is greater. The threshold of MTIP and MRING varies with the line type selected at LEN0, LEN1 and LEN2. This insures detection of the lowest level zero to one transition (-15 dB buildout) as it occurs on TTIP and TRING. T1 LINE LENGTH SELECTION Table 2 LEN2 0 0 0 0 1 1 1 1 LEN1 0 0 1 1 0 0 1 1 LEN0 0 1 0 1 0 1 0 1 OPTION SELECTED Test mode -7.5 dB buildout -15 dB buildout 0 dB buildout, 0 - 133 feet 133 - 266 feet 266 - 399 feet 399 - 533 feet 533 - 655 feet APPLICATION Do not use T1 CSU T1 CSU T1 CSU, DSX-1 Cross connect DSX-1 Cross connect DSX-1 Cross connect DSX-1 Cross connect DSX-1 Cross connect NOTE: 1. The LEN0, LEN1 and LEN2 inputs control T1 output waveshapes when TCLKSEL=0. The G.703 (CEPT) template is selected when TCLKSEL=1 and LEN0, LEN1, and LEN2 are at any state except all zeros. 022798 4/11 DS2186 DSX-1 ISOLATED PULSE TEMPLATE Figure 3 1.0 0.5 NORMALIZED ALITITUDE 0.0 -0.5 0 250 500 750 NANOSECONDS 1000 1250 NOTES: 1. Template shown is measured at the cross-connect point. 2. Amplitude shown is normalized; the actual midpoint voltage measured may be between 2.4 and 3.6 volts. 3. The corner points shown below are joined by straight lines to form the template. MAXIMUM CURVE (0, 0.05) (250, 0.05) (325, 0.80) (325, 1.15) (425, 1.15) (500, 1.05) (675, 1.05) (725, -0.07) (875, 0.05) (1250, 0.05) MINIMUM CURVE (0, -0.05) (350, -0.05) (350, 0.5) (400, 0.95) (500, 0.95) (600, 0.9) (650, 0.5) (650, -0.45) (800, -0.45) (925, -0.2) (1100, -0.05) (1250, -0.05) 022798 5/11 DS2186 OUTPUT PULSE TEMPLATE AT 2.048 MHz Figure 4 1.2 1.0 NORMALIZED AMPLITUDE 0.5 0.0 -0.2 250 NANOSECONDS 500 NOTES: 1. Unlike the DSX-1 template, which is specified at the cross-connect point, the CEPT (2.048 MHz) template is specified at the transmit line output. 2. The template shown above is normalized. The actual pulse height is cable dependent and is specified in Table 3. 3. The corner points shown below are joined by straight lines to form the template. MAXIMUM CURVE (0, 0.1) (109.5, 0.5) (109.5, 1.2) (244, 1.1) (378.5, 1.2) (378.5, 0.5) (488, 0.1) MINIMUM CURVE (0, -0.1) (134.5, -0.2) (134.5, 0.5) (147, 0.8) (244, 0.9) (341, 0.8) (353.5, 0.5) (353.5, -0.2) (488, -0.1) 022798 6/11 DS2186 CHARACTERISTICS OF T1 AND CEPT INTERFACES Table 3 CHARACTERISTIC LINE RATE LINE CODE TEST LOAD IMPEDANCE NOMINAL PEAK VOLTAGE PULSE SHAPE NOMINAL PULSE WIDTH PULSE IMBALANCE 324 ns < 0.5 dB difference between total power of positive and negative pulses. 1.544 MHz AMI1 or B8ZS 100 ohm Resistive 2.4V to 3.6 V2 T1 2.048 MHz AMI or HDB3 120 ohm Resistive (wire pair) 75 ohm Resistive (coax) 3.0V (wire pair) 2.37V (coax) -Scaled to fit templates shown- 244 ns 1) Negative peak = positive peak 5% 2) Positive width at nominal half amplitude = negative width at nominal half amplitude 5%. CEPT NOTES: 1. With a ones density of at least 12.5% and no more than 15 consecutive zeros. 2. Measured at the cross-connect (DSX-1) point; CSU applications may be 7.5 to 15 dB below these levels. 022798 7/11 DS2186 ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -1.0V to +7V 0C to 70C -55C to +125C 260C for 10C * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER Logic 1 Logic 0 Supply SYMBOL VIH VIL VDD MIN 2.0 -0.3 4.75 TYP MAX VDD+.3 +0.8 5.25 UNITS V V V (0C to 70C) NOTES 1 1 DC ELECTRICAL CHARACTERISTICS PARAMETER Supply Current Supply Current Supply Current Input Leakage Output Current @ 0.4V SYMBOL IDD IDD IDD IIL IOL -1.0 +4.0 MIN TYP 50 35 20 (0C to 70 C; VDD = 5V 5%) MAX UNITS mA mA mA +1.0 A mA NOTES 2,3 2,4 2,5 6 7 CAPACITANCE PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP MAX 5 7 UNITS pF pF (tA = 25C) NOTES NOTES: 1. All inputs except MTIP and MRING. 2. VDD=5.25V; TCLK = LCLK = 1.544 MHz; output line transformer and load as shown in Figure 2. 3. TAIS = 1 4. 50% ones density. 5. All zeros at data inputs. 6. 0.0V < VIN < 5.0V. 7. Output LF (open collector). 022798 8/11 DS2186 AC ELECTRICAL CHARACTERISTICS PARAMETER TCLK, LCLK Period TCLK, LCLK Period TCLK, LCLK Pulse Width TCLK, LCLK Pulse Width TCLK, LCLK Rise and Fall Times TPOS, TNEG Setup to TCLK Falling LPOS, LNEG Setup to LCLK Falling TPOS, TNEG Hold from TCLK Falling LPOS, LNEG Hold from LCLK Falling SYMBOL tCLK tCLK tRWH, tRWL tRWH, tRWL tR, tF tSTD tSTD tHTD tHTD 50 50 50 50 70 70 MIN TYP 648 488 324 244 (0C to 70C; VDD = 5V 5%) MAX UNITS ns ns ns ns 20 ns ns ns ns ns NOTES 1 2 1 2 NOTES: 1. T1 applications. 2. CEPT applications. AC TIMING DIAGRAM Figure 5 tCLK tRWH tRWL tF tR TCLK, LCLK tSTD TPOS, TNEG LPOS, LNEG tHTD 022798 9/11 DS2186 DS2186 TRANSMIT LINE INTERFACE 20-PIN DIP PKG DIM 20-PIN MIN 1.020 25.91 0.240 6.10 0.120 3.05 0.300 7.62 0.015 0.38 0.120 3.04 0.090 2.23 0.320 8.13 0.008 0.20 0.015 0.38 MAX 1.040 26.42 0.260 6.60 0.140 3.56 0.325 8.26 0.040 1.02 0.140 3.56 0.110 2.79 0.370 9.40 0.012 0.30 0.021 0.53 B A IN. MM B IN. MM C IN. MM 1 A D IN. MM E IN. MM F IN. MM C G IN. MM H IN. MM J IN. MM E K G F K IN. MM D J H 022798 10/11 DS2186 DS2186S TRANSMIT LINE INTERFACE 20-PIN SOIC K G PKG DIM A IN. MM B H B IN. MM C IN. MM E IN. MM 1 F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM E L IN. MM phi 20-PIN MIN 0.500 12.70 0.290 7.37 0.089 2.26 0.004 0.102 0.094 2.38 MAX 0.511 12.99 0.300 7.65 0.095 2.41 0.012 0.30 0.105 2.68 0.050 BSC 1.27 BSC 0.398 10.11 0.009 0.229 0.013 0.33 0.016 0.406 0 0.416 10.57 0.013 0.33 0.019 0.48 0.040 1.20 8 A C F phi J L 022798 11/11 |
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